IP Catalog > ARINC 429

ARINC 429 IP

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Compare 14 IP from 10 vendors (1 - 10)
  • ARINC 429 Verification IP
    • Supports ARINC SPECIFICATION 429 PART 1-17.
    • Supports all word structures and protocol necessary to establish bus communication as per the specs.
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus.
    • Supports LRU with multiple transmitters and receivers communicating on different buses.
    Block Diagram -- ARINC 429 Verification IP
  • ARINC 429 Synthesizable Transactor
    • Supports ARINC SPECIFICATION 429 PART 1-17
    • Supports all word structures and protocol necessary to establish bus communication as per the specs
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus
    • Supports LRU with multiple transmitters and receivers communicating on different buses
    Block Diagram -- ARINC 429 Synthesizable Transactor
  • ARINC 429 IP Core
    • Implements ARINC 429 Data Bus Communication Protocol.
    • Supports both Transmit and Receive functionality for ARINC 429 words.
    • Configurable data rates for flexible integration into avionics systems.
    • Provides advanced error detection mechanisms for high data integrity.
    • Bare-metal application or PetaLinux OS with associated APIs.
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 IP Core
    • ARINC 429 IP Core implements ARINC 429 standard.
    • IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces.
    • A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 IP-Core with DO-254 Package
    • Applicable Standards:
    • Configuration support per channel:
    • Technical features:
    • Supported tools:
    Block Diagram -- ARINC 429 IP-Core with DO-254 Package
  • ARINC 429 IP Core
    • Multichannel module supporting ARINC429 Receiver/Transmitter.
    • Configurable module supporting any number of receivers and transmitters (Standard with 16 receivers & 8 transmitters).
    • Configurable data rate supporting from 12.5 Kbps to 1 Mbps.
    • Parity & Gap generators & checkers for high data integrity.
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 Transmitter DO-254 IP Core
    • The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
    • The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
    Block Diagram -- ARINC 429 Transmitter DO-254 IP Core
  • ARINC 429 Receiver DO-254 IP Core
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to Bosch’s CAN Specification 2.0 (Sep 1991)
    • Time Triggered Communication (TTC) support according to ISO 11898-1 (2003-12-01)
    • Tested as specified in the ISO 16845 (2004-03-15)
    Block Diagram -- ARINC 429 Receiver DO-254 IP Core
  • ARINC 429 Tx & Rx
    • User ARINC 429 configuration
    • Programmable data rate for 100 kbsor 12.5kbs
    • Transmitter and Receiver can b eEnabled /Disabled
    • Based on vendor and technology independent VHDL code
  • ARINC 429 Synchronous Transmitter Receiver
    • 1 Independent Receivers (Rx) with FIFO
    • 1 Independent Transmitter (Tx) with FIFO
    • Decoding signals interface type
    • 16-Bit Data-bus
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