The ARINC 429 Rx IP Core implements a receiver as specified in the ARINC Specification 429 Part 1-17.
This “Mark 33 Digital Information Transfer System (DITS)” specification defines how to transfer digital data between avionics systems elements. The transmission is done over a twisted and shielded pair of wires and bi-directional data flow is not permitted. An extra twisted and shielded pair of wires is used when data is required to flow both ways.
The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
A radiation-hardened version with Triple Modular Redundancy (TMR) is also available.
Safe Core Devices provides two separate IP Cores, one for the ARINC 429 Rx Core and one for the ARINC 429 Tx Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
The ARINC 429 Rx Core is already being used in one program: a civil large airplane program, as DAL A.
Implementation Details
The following tables show some examples of implementing the A429 Rx Core in different technologies and devices. Note that the A429 Rx Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).
Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.
No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multi-cycle, false paths, etc. defined).
The synthesis and place and run has been performed with the following options:
- g_COUNTERS_SIZE : 16
ACTEL/MICROSEMI
| FPGA Type | Maximum ‘clk‘ Frequency | Logic Modules (CORE) |
|---|---|---|
| ProASIC3
(A3P015 68QFN I Std) |
73 MHz | 643 |
| IGLOO
(AGL030V5 100VQFP I Std) |
61 MHz | 631 |
| Fusion
(AFS090 180QFN I Std) |
72 MHz | 643 |
| Axcelerator
(RTAX250S 208CQFP Mil Std) |
79 MHz | SEQUENTIAL (R-cells): 120
COMB (C-cells): 264 |
ALTERA
| FPGA Type | Maximum ‘clk’ Frequency | Flip-Flops | ALUTs | ALMs | Logic Cells |
|---|---|---|---|---|---|
| MAX II
(EPM240F100I5) |
72 MHz | 116 | – | – | 254 |
| Cyclone III
(EP3C5E144I7) |
> 170 MHz | 116 | – | – | 252 |
| Stratix II
(EP2S60F484I4) |
215 MHz | 116 | 161 | 134 | – |
| Stratix III
(EP3SE110F780I3) |
> 300 MHz | 116 | 154 | 126 | – |
| Stratix IV
(EP4SGX70HF35C2) |
> 340 MHz | 116 | 154 | 125 | – |
XILINX
| FPGA Type | Maximum ‘clk‘ Frequency | Flip-Flops | 4-LUTs | Slices | Macrocells |
|---|---|---|---|---|---|
| CoolRunnerII
(XC2C128-6-TQ144) |
61 MHz | 102 | – | – | 137 |
| Spartan3
(XC3S50-4PQ208) |
118 MHz | 116 | 241 | 157 | – |
| Virtex2
(XC2V40-4FG256) |
128 MHz | 116 | 247 | 160 | – |
| Virtex4
(XC4VLX15-12SF363) |
246 MHz | 116 | 248 | 159 | – |
| Virtex5
(XC5VLX30-3FF324) |
280 MHz | 116 | – | 86 | – |
