ARINC 429 Verification IP

Overview

ARINC 429 Verification IP implements the air transport industry’s standards for the transfer of digital data between avionics systems. ARINC 429 Verification IP provides an smart way to verify the ARINC 429 standard data transmission and control interfaces between source and sink. The SmartDV's ARINC 429 Verification IP is fully compliant with ARINC SPECIFICATION 429 PART 1-17 and provides the following features.

ARINC 429 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ARINC 429 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports ARINC SPECIFICATION 429 PART 1-17.
Supports all word structures and protocol necessary to establish bus communication as per the specs.
Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus.
Supports LRU with multiple transmitters and receivers communicating on different buses.
Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself.
Supports Transmission rates at either a low speed 12.5 kHz or a high speed 100kHz.
Supports two speeds for data transmission
- Low speed operation 12.5 kHz, with an actual allowable range of 12 to 14.5 kHz.
- High speed operation is 100 kHz.
Supports bipolar and Return-to-Zero encoding format.
Supports following data types
- Binary BNR Transmitted in fractional two's complement notation
- Binary Coded Decimal BCD Numerical subset of ISO Alphabet No. 5
- Discrete Data Combination of BNR, BCD or individual bit representation
- Maintenance Data and Acknowledgement Requires two-way communication
- Williamsburg/Buckhorn Protocol A bit-oriented protocol for file transfers
Supports duplex or two-way communication in Maintenance Data and Acknowledgement between source and sink.
Glitch injection and detection
Supports all types of errors insertion/detection as given below:
- Missing SOT word
- LDU Sequence Number Error
- Parity Errors
- Word Count Errors
- CRC Errors
- Time Out Errors
Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
Status counters for various events.
Callbacks in source and sink for various events.
Built in functional coverage analysis.
FIFO depth programmable.
ARINC 429 Verification IP comes with complete testsuite to verify each and every feature of ARINC 429 specification.

Benefits

Faster testbench development and more complete verification of ARINC 429 designs.
Easy to use command interface simplifies testbench control and configuration of Source, Sink and monitor
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the ARINC 429 testcases.
Examples showing how to connect various components, and usage of Source,Sink and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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