IP Catalog > AHB Compliant Cache Controller

AHB compliant Cache controller IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (21)
Compare 21 IP from 6 vendors (1 - 10)
  • ONFI 2 NAND Flash Controller IP Compliant to JEDEC
    • The ONFI 2.3 NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.
    • Designed to support both SLC and MLC flash memories, ONFI 2.3 NAND controller IP is flexible in use and easy in implementation.
    Block Diagram -- ONFI 2 NAND Flash Controller IP Compliant to JEDEC
  • eMMC 4.51 Device Controller IP
    • Compliant to JEDEC JESD84-B45 eMMC 4.51 spec
    • Packed commands for faster processing
    • Supports cache control mechanism
    • Supports eMMC4.51 Security Protocol Commands
    Block Diagram -- eMMC 4.51 Device Controller IP
  • MIPI LLI Controller
    • The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
    • This is achieved by the low latency from the “companion” chip to the memory interface of the host chip.
    Block Diagram -- MIPI LLI Controller
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
  • 32-bit CPU IP core - ISO 26262 Automotive Functional Safety Compliant
    • 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
    Block Diagram -- 32-bit CPU IP core - ISO 26262 Automotive Functional Safety Compliant
  • Compact High-Speed 32-bit CPU Core with Level-2 Cache
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    Block Diagram -- Compact High-Speed 32-bit CPU Core with Level-2 Cache
  • 32-Bit SPARC V8 Processor
    • SPARC V8 instruction set with V8e extensions and compare-and-swap
    • Advanced 7-stage dual-issue pipeline
  • 32-bit Multiprocessor with Level-2 Cache-Coherence
    • AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
    • It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DSP/SIMD 'P' extension (draft), user-level interrupt 'N' extension, and Andes performance/functionality enhancements such as instructions for faster memory accesses, faster branch handling, and Andes Custom Extension™ (ACE) to add user defined instructions.
    Block Diagram -- 32-bit Multiprocessor with Level-2 Cache-Coherence
  • USB2.x HOST IIP
    • Compliant with USB 2.0 specification.
    • Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
    • Asynchronous Park-mode
    • Three caching models: no caching, micro-frame caching and frame caching
    Block Diagram -- USB2.x HOST IIP
  • USB2.x OTG IIP
    • Compliant with USB 2.0 specification.
    • Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
    • Asynchronous Park-mode
    • Three caching models: no caching, micro-frame caching and frame caching
    Block Diagram -- USB2.x OTG IIP
×
Semiconductor IP