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AES-GCM IP

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Compare 68 IP from 14 vendors (1 - 10)
  • Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
    • High throughput
    • Guaranteed performance with small packets
    • 128-bit and 256-bit key
    Block Diagram -- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
  • Secure-IC's Securyzr(TM) AES-GCM Ultra-Low Latency
    • High throughput: 64 GB/s (512 Gbps)
    • Ultra-low latency
    • Optional CRC support for data integrity
    Block Diagram -- Secure-IC's Securyzr(TM) AES-GCM Ultra-Low Latency
  • AES-GCM Authenticated Encrypt/Decrypt Core
    • Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
    • Implemented according to the National Institute of Standards and Technology (NIST) Special Publication 800-38D
    • NIST Certified
    • Processes 128-bit data in 32-bit blocks
    Block Diagram -- AES-GCM Authenticated Encrypt/Decrypt Core
  • AES-GCM, Extreme-Speed IP Cores for AES256-GCM Authenticated Encryption
    • High Security
    • Extremely High Throughput
    • Constant Latency
    Block Diagram -- AES-GCM, Extreme-Speed IP Cores for AES256-GCM Authenticated Encryption
  • AES-GCM, Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core
    • Moderate resource requirements: The entire XIP1111H requires approximately 21700 Adaptive Lookup Modules (ALMs) (Intel ® Cyclone ® V), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation. Contact sales@xiphera.com for ASIC resource requirements.
    • Optimized Implementation utilizing unrolling, pipelining, optimized AES S-box design, and GMAC calculation based on pipelined Karatsuba multipliers enable extremely high performance.
    • Performance: XIP1113H achieves a throughput in the tens of Gbps range, for example 65+ Gbps in Xilinx ® UltraScale+ MPSoC.
    • Standard Compliance: XIP1113H is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
    Block Diagram -- AES-GCM, Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core
  • AES-GCM, Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core
    • Compact resource requirements: The entire XIP1113B requires less than 2800 Adaptive Lookup Modules (ALMs) (Intel® Cyclone®V), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation. Contact sales@xiphera.com for ASIC resource requirements.
    • Performance: Despite its compact size, XIP1113B achieves a throughput in the Gbps range, for example 2.0 Gbps in Xilinx® Artix®-7 family.
    • Standard Compliance: XIP1113B is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
    • Test Vector Compliance: XIP1111B passes all test vectors specified in MACsec GCM-AES Test Vectors.
    Block Diagram -- AES-GCM, Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core
  • AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
    • Small size: Starting at less than 13K ASIC gates, 1.5 Gbps performance at less than 20K gates
    • Scalability to throughputs of 128 bits per clock with the capability of parallel cores at throughputs of 100 Gbps and above
    • Supports Galois Counter Mode Encryption and authentication (GCM-AES a.k.a. AES-GCM)
    • Includes AES-GCM encryption, AES-GCM decryption, key expansion and data interface
    Block Diagram -- AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
  • AES-GCM Encryption Core
    • Full Verilog core
    • Synth-time selectable number of parallel paths allows the user to balance area/bandwidth requirements
    • Synth-time selectable internal buffer sizing for area/bandwidth balancing
    • Synth-time selectable 128 or 256 bit AES encryption key size
  • AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
    • EXAMPLE CONFIGURATIONS
    • The SafeXcel-IP-63 has a scalable number of processing pipes and channels. It is available in different configurations, suitable for different applications to meet different gate count and throughput objectives.
    • • EIP-63a-c17-r
    • o single pipe, 17 channels, register based (no memories)
  • Ultra high performance AES-GCM for OTN networks
    • Cipher Modes: AES-GCM (as specified in NIST SP800-38D)
    • Compute Units: Selectable between 1, 2, 4, 8 or 16
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