Secure-IC's Securyzr(TM) AES-GCM Ultra-Low Latency

Overview

The AES-GCM Ultra-low latency crypto engine is targeted for CXL link encryption with an implementation of the AES-GCM algorithm compliant with the NIST SP 800-38D standard. The unique architecture enables high throughput while maintaining an optimal resource usage.

The AES-GCM (Galois Counter Mode) is an authenticated encryption algorithm which combines the AES counter mode for encryption and the Galois field multiplier for the authentication. The encryption and authentication occur in parallel to enable high throughput.

The AES-GCM is the only authenticated encryption algorithm recommended by NIST enabling very high throughput. In addition, it also offers ultra-low latency:
• 0 clock cycle for encryption/decryption (combinational path)

In addition, it supports CXL 2.0. One of many new great features that comes with CXL 2.0 is the support for single level switching to enable fan-out to multiple devices. This will enable many devices in a platform to migrate to CXL, while maintaining the backward compatibility and the low-latency characteristics of CXL.


For other AES solutions, please see dedicated product sheets: AES Multi-Purpose (SCZ_IP_BA411e), AES-XTS Multi-Booster (SCZ_IP_BA416) and AES-GCM Multi-Booster (SCZ_IP_BA415).

Key Features

  • High throughput: 64 GB/s (512 Gbps)
  • Ultra-low latency
  • Optional CRC support for data integrity
  • 128-bit and 256-bit key
  • NIST SP 800-38D compliant
  • Best trade-off between area and performance

Benefits

  • The AES-GCM is the only authenticated encryption algorithm recommended by NIST enabling very high throughput. In addition, it also offers ultra-low latency with 0 clock cycle for encryption/decryption (combinational path)

Block Diagram

Secure-IC's Securyzr(TM)  AES-GCM Ultra-Low Latency Block Diagram

Applications

  • CXL 2.0
  • PCI Express 5.0

Deliverables

  • Netlist or RTL
  • Scripts for synthesis
  • Self-checking TestBench based on FIPS vectors
  • Datasheet
  • Integration guide

Technical Specifications

Maturity
Silicon proven
Availability
Now
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Semiconductor IP