5g IP

The XC21 is the most efficient vector DSP core available today for communications applications.
The XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications.
Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices

The XC23 is the most powerful DSP core available today for communications applications. The-XC23 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, more efficient wireless infrastructure
Targeted for 5G and 5G-Advanced workloads, the XC23 has two independent execution threads and a dynamic scheduled vector-processor, providing not only unprecedented processing power but unprecedented utilization on real-world 5G multitasking workloads.

The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data.
Its flexible data path is suitable to scale from 100 Gbps to 2.4 Tbps to provide a tailored engine with minimal area for your application.
The FIFO-like data interface makes it possible to perform frame processing for many different protocols, including MACsec, IPsec, and OTN security.

Comprehensive Support: All PRACH formats and configuration indexes described in 3GPP 38.211 are fully supported.
Versatile Sequences: Length-139 and length-839 sequences are included.
Frequency Multiplexing: Capable of decoding up to 8 frequencies multiplexed PRACHs.

The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.

Complete implementation of the relevant 3GPP standards
Improved spectral efficiency across low SINR range against industry-standard simulation toolbox

The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
PDSCH encoder has a configurable IQ parallelism for improved performance per clock.
The functions included are CRC, Segmentation, LDPC encode, Rate matching, Integrated HARQ, Concatenation, Scrambling and Modulation.

5G IP