IP Catalog > 100GBase-KR/CR4 PCS

100GBase-KR/CR4 PCS IP

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Compare 9 IP from 4 vendors (1 - 9)
  • Ethernet PHY IP
    • Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
    • Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
    • DSP-based architecture using high-performance ADC/DAC for RX/TX
    Block Diagram -- Ethernet PHY IP
  • Intel® Agilex™ 7 F-Tile Ethernet Hard IP
    • The Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates from 10G to 400G, compatible with IEEE 802.3 specification, and other related Ethernet Consortium specifications.
    Block Diagram -- Intel® Agilex™ 7 F-Tile Ethernet Hard IP
  • Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
    • The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium
    • The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.
    Block Diagram -- Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
  • Simulation VIP for Ethernet up to 800G
    • 800Gbps Interfaces
    • 800Gbps Ethernet interfaces based on Ethernet Technology Consortium supports:
    • 800GMII
    • 800GBase-R Dual-PCS 32 lanes (25Gb/s)
    Block Diagram -- Simulation VIP for Ethernet up to 800G
  • Ethernet TSN Verification IP
    • Supports Time Sensitive transmission of data over Ethernet networks
    • Full support for IEEE 802.1Qat
    • Full support for IEEE 802.1QAV
    • Full support for IEEE 802.1Q
    Block Diagram -- Ethernet TSN Verification IP
  • Ethernet - up to 800G Verification IP
    • Supports 2.5G and 5G Speeds as per 802.3cb
    • 2.5GBASE-KX
    • 5GBASE-KR
    • 2.5GBASE-T
    Block Diagram -- Ethernet - up to 800G Verification IP
  • Ethernet 40G,100G Verification IP
    • Supports 1G
    • Supports GMII
    • Supports TBI (i.e Output of 8b/10b PCS)
    • Supports SGMII(10M/100M/1000M) as per specification 1.8
    Block Diagram -- Ethernet 40G,100G Verification IP
  • Ethernet Synthesizable Transactor
    • Supports Full MII/RMII/SMII TX/RX functionality
    • Supports Mac control and data frames support
    • Ability to generate VLAN tagged and Priority tagged frames
    • Supports Pause frame detection and generation
    Block Diagram -- Ethernet Synthesizable Transactor
  • Ethernet 100G Synthesizable Transactor
    • Supports 100G as per 802.3ba and 802.3bj:
    • Supports CGMII
    • Supports 100GBase-KR10/
    • Supports 100GBase-KR4
    Block Diagram -- Ethernet 100G Synthesizable Transactor
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