Ethernet 40G,100G Verification IP

Overview

The Ethernet 40G,100G Verification IP is compliant with IEEE 802.3ba and IEEE 802.3bj specifications and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet 40G,100G interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. Ethernet 40G,100G verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

Ethernet 40G,100G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Ethernet 40G,100G Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 1G

Supports GMII
Supports TBI (i.e Output of 8b/10b PCS)
Supports SGMII(10M/100M/1000M) as per specification 1.8
Supports QSGMII as per specification 1.2
Supports USGMII as per specification 3.0 and 3.1(5G and 10G)
Supports RGMII(10M/100M/1000M),RTBI as per specification 2.0
Supports 1000Base-KX
Supports 1GBASE-SX and 1GBASE-LX
Supports clause 73 backplane auto-negotiation for 1000Base-KX
Supports clause 37 auto-negotiation
Supports SGMII auto-negotiation
Supports QSGMII auto-negotiation
Supports USGMII auto-negotiation and packets
Supports full duplex and half duplex of operation

Supports 40G as per 802.3ba

Supports XLGMII
Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4
Supports XLAUI
Supports FEC
Supports scrambler
Supports backplane auto-negotiation
Supports Link training

Supports 100G as per 802.3ba and 802.3bj

Supports CGMII
Supports 100GBase-KR10/100GBase-CR10/100GBase-SR10
Supports 100GBase-ER4/100GBase-LR4
Supports 100GBase-KR4
Supports 100GBase-KR2
Supports 100GBase-KR
Supports 100GBase-R
Supports 100GBASE-KP4 with PMA enable.
Supports Gray coding and Precoding as per Spec IEEE 802.3-2018
Supports CAUI_4 and CAUI10
Supports RS_FEC(clause 91) and Fire-code FEC
Supports scrambler
Supports backplane auto-negotiation
Supports Link training

Supports Pause frame generation and detection.
Supports MDIO slave and master model as per Clause 22 and Clause 45
Glitch insertion and detection
PCS to Serdes interface supports all widths
Supports CDR for serial protocols
Supports the upper layer protocols
Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
Full support for IEEE 1588-2002 and IEEE 1588-2008
Supports G.999.1 Interface
Ethernet Verification IP comes with complete UNH Test suite
Supports all types of TX and RX errors insertion/detection at each layer.

Oversize, undersize, inrange, out of range Packet size errors
Missing SPD/EPD/SFD framing errors
SFD on wrong lane
CRC Error
Lane skew insertion
Invalid /D/ and /K/ character injection
Variable preamble and IPG insertion
Invalid block code insertion
Sync bit corruption
FEC error injection
Scrambler error injection

Comes with Tx BFM,Rx BFM, and Monitor.
Monitor supports detection of all protocol violations.
Built in coverage analysis.
Status counters for various events in bus

Benefits

Faster testbench development and more complete verification of Ethernet 40G,100G designs.
Easy to use command interface simplifies testbench control and configuration of Ethernet 40G,100G TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite (UNH) containing all the Ethernet 40G,100G testcases.
Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info