General Purpose Input / Output Controller (GPIO)

Overview

The GPIOmodule is a general purpose input/output controller, offering some unique features that eases system integration and use.

Each GPIO port can be configured for input, output or bypass mode. Output data can be set in one access or single or multiples bits can be set or cleared. Every GPIO port can serve as an interrupt source and has its own configuration options:

Level sensitive, single edge triggered or level change
Active high or low respectively rising edge or falling edge
Individual interrupt enable register and status flags

An industry standard AMBA APB host interface simplifies system embedding. An AXI Lite host interface is available on request.

Implementation Options

Following synthesis options are available using top-level generics:

APB bus width (8/16/32 bit)
Number of ports
CPU readback enable

Key Features

Up to 32 ports
Each port can be input, output or bypass
Data set or bitwise set and clear control
Input data synchronization
Flexible interrupt generation for each GPIO pin
Supports synchronous bus interfaces such as AMBA APB version 2.0
Full synchronous design
Synthesis Options

Benefits

For gate-count optimization, the core can be configured to disable the configuration register read-back path. Synthesis options are included to use the core in 8, 16 and 32-bit systems. The number opf ports is selectable as well.
With a separate APB wrapper, the core can be used in ARM subsystems.

Block Diagram

Applications

Industrial control
System-on-Chip
Peripheral Logic
Embedded Systems

Deliverables

VHDL or Verilog RTL Source Code
Functional Testbench
Synthesys Script
Data Sheet
User Guide
Hotline Support by means of phone, fax and e-mail

Technical Specifications

Foundry, Node

Technology independent

Maturity

Proven in many ASIC and FPGA Technologies

Availability

now

Request Info