SD/eMMC PHY IP

Compare 45 SD/eMMC PHY IP from 8 vendors (1 - 10)

eMMC/SD/SDIO Combo IP
- The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of applications
- This IP integrates a host controller and PHY, enabling seamless communication with eMMC, SD, and SDIO devices
- When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes
TSMC N3P 1.8V IO Platform supporting cells
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
SD/EMMC PHY
- Include 1 clock, 1 bi-directional CMD, and 4 bi-directional DATA channel
- Design in GLOBALFOUNDRIES 22nm FDX process
- Data rate range: 50M~104MB/s
- Supports up to 208MHz clock
M31 eMMC/SDIO at HLMC 28HKC+ Process
- Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
- Consisting of driver, receiver & pull-up/down resistors
- Power-sequence free
- Provides multi-driving-strength selection
M31 eMMC/SDIO at TSMC 40LP Process
- Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
- Consisting of driver, receiver & pull-up/down resistors
- Power-sequence free
- Provides multi-driving-strength selection
M31 eMMC/SDIO at TSMC 28HPC+ Process
- Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
- Consisting of driver, receiver & pull-up/down resistors
- Power-sequence free
- Provides multi-driving-strength selection
SD 4.0 UHS-II PHY in TSMC 40LP
- Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II
- Specification Volume 1: System and Protocol”
- Per lane data rate between 390Mb/s to 1.56Gb/s
- Supports peak interface speed of 3.12Gb/s (Half-duplex); 1.56Gb/s in Full-duplex mode
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
- • Suitable for Transmitter, Receiver, and Data Strobe pins
- VCORE Pre driver voltage
- VCCQ Post driver voltage
- TJ Junction temperature
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
- Silicon proven, fully compliant core
- Premier direct support from IP core designers
- Easy-to-use industry standard test environment
TSMC N4P SD/eMMC PHY North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution