SD/eMMC PHY IP

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Compare 32 SD/eMMC PHY IP from 8 vendors (1 - 10)
  • eMMC 5.1 Nex Bus Driver
    • eMMC 5.1 Nex Bus Driver is a production-ready software stack for eMMC 5.1 Host Controller IP that is used to connect eMMC devices.
    • The eMMC 5.1 stacks can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- eMMC 5.1 Nex Bus Driver
  • eMMC 5.1 HS400 PHY
    • The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications.
    • This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.
    Block Diagram -- eMMC 5.1 HS400 PHY
  • eMMC 5.1 Device I/O Pad
    • The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50 specification. It is backward compliant with eMMC4.51 and earlier versions of the specifications.
    • This allows the designers of the SoC to easily support the EMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 hosts.
    Block Diagram -- eMMC 5.1 Device I/O Pad
  • eMMC/SD/SDIO Combo IP
    • The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of applications
    • This IP integrates a host controller and PHY, enabling seamless communication with eMMC, SD, and SDIO devices
    • When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes
    Block Diagram -- eMMC/SD/SDIO Combo IP
  • TSMC N3P 1.8V IO Platform supporting cells
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P 1.8V IO Platform supporting cells
  • SD/EMMC PHY
    • Include 1 clock, 1 bi-directional CMD, and 4 bi-directional DATA channel
    • Design in GLOBALFOUNDRIES 22nm FDX process
    • Data rate range: 50M~104MB/s
    • Supports up to 208MHz clock
    Block Diagram -- SD/EMMC PHY
  • M31 eMMC/SDIO at HLMC 28HKC+ Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at HLMC 28HKC+ Process
  • M31 eMMC/SDIO at TSMC 40LP Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 40LP Process
  • M31 eMMC/SDIO at TSMC 28HPC+ Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 28HPC+ Process
  • TSMC N4P SD/eMMC PHY North/South Poly Orientation
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N4P SD/eMMC PHY North/South Poly Orientation
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