The JESD204D Controller IP from Comcores is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D IP core supports line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and includes full backwards compatibility with 32.5 Gbps JESD204C.1 64b 66b link layer and 16 Gbps JESD204B 8b 10b link layer.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.
JESD204D
Overview
Key Features
- Richly Featured
- Line rates up to 116 Gbps
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs standard required scrambling
- RS-FEC (544,514), RS-FEC (528,514), RS-FEC (272,258), FEC (144,130) and FEC (136,130)
- RS-FEC error detection
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1 and 3)
- Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- Strong engineering support for bring-up
- Solid
- Silicon proven
- Lint/CDC optimized
- UVM regression tested
- Interoperability tested with leading PHY/SerDes vendors
- Silicon Agnostic
- Targeting both ASICs and FPGAs
Block Diagram
Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Test Report
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers
Technical Specifications
Maturity
Mature
Availability
Available