Industry First, Silicon Proven, 116 Gbps per lane IP core, backed by a complete portfolio of verification tools, PHY interop, and demos
The JESD204D Controller IP is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D IP core supports line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and includes full backwards compatibility with 32.5 Gbps JESD204C.1 64b66b link layer and 16 Gbps JESD204B 8b10b link layer.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.
JESD204D controller IP is fully compliant with the revised D standard of JESD204, which is characterized with support for Data interface speeds of up to 116 Gbps with PAM4 encoding as well as three types of channels, Extra Short Reach (XSR), Medium Reach (MR), and Long Reach (LR) and the RS-FEC link layer
