The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b 10b encoding. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
JESD204B
Overview
Key Features
- Delivering Performance
- Designed to JEDEC JESD204B specification
- Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 25 Gbps)
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Checks link configuration data with user selected parameter values during initial lane synchronization sequence
- 8b 10b encoding
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1, and 2) on the 8b10b link layer
- Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of SerDes PHY solutions
- Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
- Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Benefits
- Designed in generic Verilog
- Silicon Agnostic- test on FPGA and take to ASIC flow
- JESD204B IP has been interoperability tested with a variety of data converters and with key providers of PHY/SerDes solutions.
- Interfaces directly to Xilinx
- Easy configuration for either RX or TX operation
- Mapper/de-mapper functionality included
- Modular design with highest degree of flexibility
- Delivering 12.5 Gbps lane speeds on up to 8 lanes
- Deterministic Latency enables use for delay sensitive applications
Block Diagram
Applications
- High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
Deliverables
- Deliverables
- The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Test Report
- Synopsys SGDC Files
- Synopsys Lint, CDC and Waivers
Technical Specifications
Maturity
Mature
Availability
Available