Industry Leading, Silicon Proven, 16 Gbps per lane IP core, backed by a complete portfolio of verification tools, PHY interop, and hardware demos
The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b 10b encoding.
The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
JESD204B delivers all the features of the standard. The solution includes separate RX, TX modules containing the link layer and transport layer.
Gearboxes are included to enable easy interfacing to any SERDES width. Chip Interfaces JESD204 IP design can include Link Layers from B, C and D versions of the standard making the final solution more flexible and compatible with more devices.
The IP is interoperability tested with leading PHY and data convertor vendors, Silicon proven across all major fabrication nodes and plants, and regression tested to 100% coverage.
