DDR6 Controller IP for UMC

Compare 89 DDR6 Controller IP for UMC from 4 vendors (1 - 10)

Denali High-Speed DDR PHY for UMC
- LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
- I/O pads with impedance calibration logic and data retention capability
- Optional clock gating available for low-power control
- Multiple PLLs for maximum system margin
DDR multi PHY
- ?Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
- ?Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
- ? Operating range of DC to 200MHz in Mobile DDR mode
- ? PHY Utility Block (PUBL) component
LPDDR4 multiPHY V2 in UMC (28nm)
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
- Maximum data rate is process technology dependent
- Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
DDR3/2 PHY
- ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
- ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
- ? Scalable performance from DDR2-667 through DDR3-1600
- ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps
DDR4 multiPHY in UMC (28nm)
- Low latency, small area, low power
- Compatible with JEDEC standard DDR4 up to 2667 Mbps
- Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
- Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process
DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process