DDR4 multiPHY in UMC (28nm)

Overview

The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), and system-in-package applications requiring high-performance DDR4/DDR3/DDR3L/DDR3U/LPDDR2/LPDDR3 SDRAM interfaces operating at up to 2667 Mbps. The Synopsys DDR4 multiPHY is ideal for systems that require high DDR3/4 performance and also may require compatibility with
the latest mobile SDRAMs (LPDDR2 and LPDDR3) for chips targeting multiple applications with varying performance requirements.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4 multiPHY is provided as a hard DDR PHY that is primarily delivered as GDSII and includes the application-specific I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4 multiPHY. The DDR4 multiPHY includes a DFI 3.1 interface to the memory controller and can be combined with any of Synopsys’ universal memory or protocol controllers for a complete DDR interface solution.

Key Features

Low latency, small area, low power
Compatible with JEDEC standard DDR4 up to 2667 Mbps
Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
Compatible with JEDEC standard LPDDR3 SDRAMs up to 2133 Mbps
DFI 3.1 compliant interface to the memory controller
Support for 4-bit, 8-bit, 16-bit and 32-bit wide SDRAMs
Support for SDRAM components soldered directly to PCB
Support for DDR4 and DDR3 UDIMMs and RDIMMs
Data path width scales in 8-bit increments from 8 bits to 72 bits
Support for partially populated interfaces
Support for 1, 2, 3, or 4 memory ranks
Support for Shared AC mode that permits one address and command channel to be time division multiplexed between independent data channels
Capability to be trained for two distinct frequencies to permit fast changes between two frequencies
Voltage and temperature compensated delay lines used for:
Support for the PHY to be distributed around a chip
Support for 28-nm poly orientation rules
Includes the PHY Utility Block (PUB)
At-speed loopback testing on both the address and data channels
MUX-scan ATPG (stuck-at SCAN)

Benefits

Supports JEDEC standard DDR4, DDR3, DDR3L (1.35V DDR3) , DDR3U (1.25V DDR3), LPDDR2, and LPDDR3 SDRAMs
High-performance DDR PHY supporting data rates from 0 to 2667 Mbps
Per-bit deskew for both read and write data paths
Per-bit deskew for address/command bus when used with LPDDR3 SDRAMs
Designed for rapid integration with Synopsys Universal Protocol or Memory Controllers for a complete DDR interface solution
Includes application-specific DDR I/Os including programmable drive strength and On-Die Termination (ODT)
DFI 3.1 compliant controller interface

Applications

Data centers (networking and storage)
Digital home
Mobile multimedia
Wireless connectivity
Digital office

Deliverables

Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files, Sample Verification Environment, PHY Data Book, Physical Implementation Guide, App Notes, Verification Guide, Installation Guide, Implementation Checklist
The PHY Utility Block includes Verilog Code, Synthesis/STA constraints and scripts, Sample Verification Environment, Data Book
DDR PHY Compiler

Technical Specifications

Foundry, Node

UMC 28nm - HPC

Maturity

Available on request

Availability

Available

UMC

Pre-Silicon: 28nm

Request Info