Clock Synthesizer IP for UMC
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Fractional-N Frequency Synthesizer (40nm - 110nm)
- Fractional/Integer-N frequency synthesizing.
- Spread spectrum clock generation (SSCG) function. (TSMC 40nm (CLN40ULP), UMC 55nm(LP) only)
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Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
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NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x000D_
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Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
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Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
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Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process