Analog IP for UMC
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Analog IP
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1,258
Analog IP
for UMC
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Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
- TSMC 90nm general purpose 1.2V CMOS process
- Single 1.2V supply
- 20 to 200 Mspls/s scalable sampling rate
- 0.5 Vp_diff input dynamic range
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CC-100IP-MB Electric Vehicle Mileage Booster IP
- Extends EV Driving range by 10%
- Extends the driving and Biking Range of Electric Vehicles from 16 to 30 Miles
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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10-Bit 100MS/s 1.8V 66mW ADC, CMOS 0.18µm
- UMC 180nm 1.8V CMOS process with MIM capacitors (optional)
- Single 1.8V supply
- up to 100 Mspls/s sampling rate
- 2Vpp_diff input dynamic range
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High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N digital PLL architecture, using an LC-tank oscillator
- Ultra-low jitter and ultra-low phase noise
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in UMC40LP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.02 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
