Receiver/Transmitter IP for TSMC
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Receiver/Transmitter IP
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14
Receiver/Transmitter IP
for TSMC
from 3 vendors
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1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
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1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
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2.5 Gbps Transceiver core
- 1.6 to 2.5 Gbps operation
- 1.8V power supply, CMOS design
- Low power dissipation
- Minimal external components
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MIPI D-PHY/sub-LVDS/CMOS1.8 combo Transmitter 2.5G/800Mbps 8-Lane
- MIPI DPHY v1-2 / MIPI CSI2 compliant
- Differential signal of almost CIS serial outputs support
- Xtal Input Clock Frequency Selectable: 24 - 72MHz
- Input Clock Frequency:
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Camera SLVS-EC/MIPI D-PHY/sub-LVDS/CMOS1.8 combo Receiver 2.4G/2.5G/800Mbps/166MHz 8-Lane
- SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
- Supporting for four kind Differential Input Signals
- Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
- Maximum Input Clock Frequency ~1.25GHz, Maximum Input Data Transfer Rate ~2.5Gbps
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Camera SLVS-EC/MIPI D-PHY/CMOS1.8 combo Receiver 2.4G/2.5G/166MHz 8-Lane
- SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
- Supporting for four kind Differential Input Signals
- Xtal Input Clock Frequency Selectable
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Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane
- SLVS-EC ver.1.2 compliant
- Supporting for four kind Differential Input Signals
- Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
- Maximum Input Clock Frequency ~400MHz (sub-LVDS)
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MIPI D-PHY Transmitter 2.5Gbps 4-Lane
- MIPI-DPHY v1-2 / MIPI CSI2 compliant
- TPSCo 65nm BSB
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Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps
- MIPI DPHY v1-1/MIPI CSI/TIA/EIA-644 LVDS/SLVS-400 compliant
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Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)