OTP IP for TSMC

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7

Fully compatible with TSMC 0.18µm mixed-signal process
Low voltage: 1.8 V ± 10% read and 3.6 V ± 5% program
High speed: 10-µs program time per bit, and 30-ns cycle time to read 8 bits at a time
Asynchronous input and latched output

Fully compatible with TSMC 0.18um 1.8V/3.3V Mixed-Signal, General Purpose process
Wide voltage range: 1.05-3.6 V read voltage and 3.6-3.9 V program voltage
Speed: 9-15.3 µs program time per bit, & 1000-ns read cycle time (1 MHz, max.), 8-bit outputs at a time
Asynchronous mode with output latches

Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.