4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process

Overview

The ATO4608X12TS040ULP7ZA is organized as 4608 x 12 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 40nm ULP standard CMOS core logic process. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.

Key Features

Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.
Asynchronous mode with output latches
Deep sleep by bringing VDD down to 0 V for SoC power saving
Built-in test mode support
Built-in fuse protection circuits
Wide temperature range: -40-125 °C read and -40-125 °C program

Benefits

Small IP size
Low program voltage/current
Low read voltage/current
High reliability
Silicon characterized and qualified

Deliverables

Datasheet
Verilog behavior model and test bench
Timing library
LEF File
Phantom GDSII database

Technical Specifications

Foundry, Node

TSMC 40ULP 0.9V/2.5V Process

Maturity

Silicon Proven & In Production

Availability

Now

TSMC

Silicon Proven: 40nm LP

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