subLVDS IP for TSMC
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subLVDS IP
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23
subLVDS IP
for TSMC
from 2 vendors
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10)
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Library of LVDS IOs cells for TSMC 65LP
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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Library of LVDS IOs cells for TSMC 40LP
- TSMC 40 LP
- 2.5V/1.1V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane
- SLVS-EC ver.1.2 compliant
- Supporting for four kind Differential Input Signals
- Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
- Maximum Input Clock Frequency ~400MHz (sub-LVDS)
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Camera MIPI D-PHY v1-1 1.5Gbps / sub-LVDS combo Receiver 4-Lane
- MIPI D-PHY v1-1 / MIPI CSI2 compliant
- Supporting for four kind Differential Input Signals:
- Maximum Input Clock Frequency: ~750MHz
- Maximum Input Data Transfer Rate: ~1.5Gbps
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MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane
- MIPI DPHY v1-1 / MIPI CSI2 compliant
- Differential signal of almost CIS serial outputs support
- Input Clock Frequency:
- (sub-LVDS mode Clock Generator Input) SCK=~1000MHz
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TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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TSMC 65LP 2Gb/s bidirectional LVDS IO cell
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Standard-compliant to TIA/EIA-644-A-2001
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TSMC 65LP 2Gb/s TX LVDS IO cell
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
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TSMC 65LP 2Gb/s RX LVDS IO cell
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
- Standard-compliant to TIA/EIA-644-A-2001
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TSMC 65GP Combo IO with 2Gb/s LVDS and CMOS GPIO
- TSMC 65 GP
- 2.5V/1.0V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
- Built-in, low parasitic ESD protection