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RAM IP for TSMC

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Search (22)
Compare 22 RAM IP for TSMC from 8 vendors (1 - 10)
  • Ultra Low Power Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 22ULL
  • Ultra Low Voltage Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 22ULL
  • Ultra Low Power Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 40ULP
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 40ULP
  • Memory Compilers
    • Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.
  • Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
    • Synchronous read/write operation
    • Low leakage current and lower operation power consumption
    • Minimum metal layer requirement: 4/3 metal layers
    • High density layout structure and small area design
  • High-Density eMRAM Compiler TSMC 22ULL
    • eMRAM compiler enabling low-power designs requiring high memory capacity
  • GCRAM, the highest-density on-chip embedded memory in standard CMOS
    • High-density bitcell offering up-to 2X area reduction over high-density 6T SRAM.
    • Full logic compatibility with standard CMOS, no additional process steps or cost.
  • Single Port SRAM compiler - Memory optimized for ultra high density and low power - compiler range up to 576 k
    • Configuration
    • SVT transistors for memory periphery
    • HD HVT Pushed rule bit cell from foundry
    • Smart periphery design
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