RAM IP for TSMC
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RAM IP
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88
RAM IP
for TSMC
from 9 vendors
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Ultra Low Power Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Power Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
- Ultra Low dynamic power
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1.Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2.Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery