DDR3 IP for TSMC
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DDR3 and DDR4 Controller and PHY on TSMC 12nm
- This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
- Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
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DDR4/3 PHY - TSMC 16FFC
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
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DDR4/3 PHY - TSMC 16FF+GL
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
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DDR4/3 PHY - TSMC 12FFC18
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
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DDR4 PHY - TSMC N7
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
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LPDDR PHY
- Application-optimized configurations for fast time to delivery and lower risk
- Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
- I/O pads with impedance calibration logic and data-retention capability
- Fine-grain custom delay cell for delay tuning
- Internal and external datapath loop-back modes
- RX and TX equalization for heavily loaded systems
- Programmable per-bit (PVT compensated) deskew on read and write datapaths