Interface IP for TSMC
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Interface IP
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1,201
Interface IP
for TSMC
from 47 vendors
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TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
- Supports DDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
- Up to 72 bits wide and up to 4 ranks
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LPDDR5X DDR Memory Controller
- JEDEC LPDDR5X/LPDDR5 devices compatible
- Data rates up to 8533Mbps
- Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
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250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- Layout for wirebond packaging
- Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
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125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI for C-PHY specification Version 1.2
- Compliant to MIPI for D-PHY specification Version 1.2
