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General Purpose PLL IP for TSMC

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Compare 203 General Purpose PLL IP for TSMC from 18 vendors (1 - 10)
  • 1.7GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 850MHz - 1700 MHz
    • Output frequency range : 850MHz -1700 MHz
    • Input frequency range : 9.6MHz - 216MHz
    Block Diagram -- 1.7GHz Multiplying PLL on TSMC 28nm
  • 5GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 2500MHz - 5000 MHz
    • Output frequency range : 1250MHz - 2500 MHz
    • Input frequency range : 12MHz - 320 MHz
    Block Diagram -- 5GHz Multiplying PLL on TSMC 28nm
  • 1.8GHz SSCG PLL on TSMC 28nm HPC+
    • Including Loop-filter
    • VCO operating range : 900MHz - 1800 MHz
    • Output frequency range : 900MHz-1800 MHz
    • Input frequency range : 12MHz - 192MHz
    Block Diagram -- 1.8GHz SSCG PLL on TSMC 28nm HPC+
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Entirely core voltage powered, needs no analog supply voltage
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
  • Low Power PLL for TSMC 40nm ULP
    • Wide range M, P, and N integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Input frequency range 1.4MHz – 32MHz.
    • 18pS RMS cycle to cycle jitter.
    • Lock-detect function.
    • Optional bypass function.
    Block Diagram -- Low Power PLL for TSMC 40nm ULP
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
  • Wide Range Programmable Integer PLL on TSMC CLN80GC
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN80GC
  • Wide Range Programmable Integer PLL on TSMC CLN5A
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Small area footprint
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN5A
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