Deskew PLL IP for TSMC
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192
Deskew PLL IP
for TSMC
from 4 vendors
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Wide-Range Low-Area Digital PLL in TSMC 28HPM
- TSMC 28HPM
- Wide Range: 40kHz to 4 GHz
- Size: <0.0mm2
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Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Process portable
- Proven (65nm to 3nm)
- Full SCAN testable
- Core voltage supply
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TSMC CLN90LP 90nm Deskew PLL - 120MHz-600MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90LP 90nm Deskew PLL - 60MHz-300MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90LP 90nm Deskew PLL - 240MHz-1200MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90GT 90nm Deskew PLL - 250MHz-1250MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90GT 90nm Deskew PLL - 125MHz-625MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90GT 90nm Deskew PLL - 500MHz-2500MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90GOD 90nm Deskew PLL - 220MHz-1100MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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TSMC CLN90GOD 90nm Deskew PLL - 110MHz-550MHz
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.