USB 3.0 IP for SMIC
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USB 3.0 IP
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USB3.0 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
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USB 3.0 PHY
- Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
- Supports 5.0 GT=s serial data transmission rate
- Supports 16- or 32-bit parallel interface
- Supports PCLK as PHY output
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CSMC 0.13um USB 1.1 PHY
- Complies with the USB1.1 standard
- CSMC 0.13um, 1.2v/3.3v power supply, 1P6M logic process
- Uses digital input/output to transmit or receive USB cable data
- Supports 12Mbit/s full speed and 1.5Mbit/s low speed serial data transmission
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USB 3.0 PHY
- 5-Gbps SuperSpeed data transmission rate through 3-m USB 3.0 cable
- Spread Spectrum clock (SSC) generation and absorption
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USB 3.0 PHY in SMIC (110nm, 65nm, 40nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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USB 3.0 femtoPHY in SMIC (28nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
- Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
- Backward compatible with 1.5Gbps, 3.0bps for SATA
- Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4 interface specification
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SMIC 28nm USB3.0 Dual Role PHY/Type-C
- 5-Gbps SuperSpeed data transmission rate through 3-m USB3.0 cable