Power Management IP for SMIC

Compare 97 Power Management IP for SMIC from 13 vendors (1 - 10)

Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
- Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
- Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
- Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
- Cost efficient solution compared to external Power Management.
Digital Cell Library SMIC
- Compact standard cell library targeting a wide range of foundries and processes
- Customized for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
- Power Management library for low-power designs
- Timing models for customizable range of PVT
Bandgap Voltage / Current Reference SMIC
- Input Voltage Range: PDK VddIO
- Programmable Output Voltage Range
- Untrimmed Accuracy: 5%
- Trimmed Accuracy (single point trim): 0.5%
Power-On-Reset SMIC
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
Linear LDO Low-Dropout Voltage Regulator SMIC
- Input Voltage Range: PDK VddIO
- Programmable Output Voltage Range
- Current Load: <1mA to 100mA
- PSRR
Power On Reset
- Input threshold 2VT.
- Reset and reset bar output logic levels.
- Minimum 8uS reset pulse for any power rise time.
- 1µA typical supply current.
Core Voltage Regulator
- Input voltage range 3.0V – 3.3V.
- Output voltage 1.2V or 1.8V ±4%.
- Output short circuit protection.
Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
- Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
- Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
- Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
- Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
LDO
180nm 5V Bandgap
- 2.5V-5.5V operation.
- 3? 4% untrimmed voltage reference accuracy.
- 2% variation over -40ºC to 125ºC after trimming.
- 70dB low frequency PSRR.