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Serdes IP for Samsung

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Compare 8 Serdes IP for Samsung from 3 vendors (1 - 8)
  • Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
    • The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.
    Block Diagram -- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
  • Extended Long-Reach (XLR) Multi Standard SerDes (MSS) IP
    • The UltraAthenaCORE Extended Long-Reach (XLR) Multi Standard SerDes (MSS) IP is a high-performance, area and latency optimized, DSP-based PHY.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 10 Gbps to 224 Gbps, supporting diverse protocols such as 10/25/50/100/200 Gbps Ethernet and UALink.
  • Long-Reach (LR) Multi-Standard-Serdes (MSS) IP
    • The AthenaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the vendor product portfolio.
    • It is a highly configurable IP that supports the most leading edge NRZ, PAM and Coherent data center standards and applications from 10Gbps to 224Gbps for Ethernet, PCIe and CXL.
  • PCI Express Gen5 SERDES PHY on Samsung 8LPP
    • Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.38 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen4 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.32 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.266 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • 28G LR Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
    • Optimized for low-power operation and north/south die-edge placement
    • Duplex Lane configurations of x4 and x1
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