Chiplet and D2D IP for Samsung

Compare 9 Chiplet and D2D IP for Samsung from 3 vendors (1 - 9)

Intra-Panel TX PHY - 28nm, 14nm, 8nm
- The Intra-panel TX PHY IP is an advanced chip-on-glass (ACOG) and chip-on-film (COF) transmitter embedded into the timing controller for TFT-LCD panels.
- This technology enables a single chip to support multiple display interfaces, reducing system costs and complexity.
- It also provides higher data transfer rates, lower power consumption, and compatibility with a wide range of devices.
UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-A PHY for Advanced Package (x64) in SS SF4X, North/South Orientation with 8collumn module configuration
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-A (Gen2) PHY for Advanced Package (x64) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange