General-Purpose I/O (GPIO) IP for GLOBALFOUNDRIES

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Compare 35 General-Purpose I/O (GPIO) IP for GLOBALFOUNDRIES from 6 vendors (1 - 10)
  • 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
    • A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
    • This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function.
    Block Diagram -- 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
  • 3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
    • A 3.3V wire-bond I/O library, a 1.2V ODIO and 5V tolerant ODIO.
    • This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology.
    • The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter.
    Block Diagram -- 3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
  • 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
    • A GlobalFoundries 180nm BCD Lite Wirebond GPIO library with tri-state out- put driver, schmitt trigger receiver and associated ESD.
    • This silicon-proven, wirebond library in GlobalFoundries 180nm BCD lite is a specialty I/O similar to Soundwire.
    • Featuring a 1.5V to 3.3V GPIO, as well as a tri-state output driver, an analog test point switch, and 7V OTP mode.
    Block Diagram -- 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
  • General IO at GF 28SLP-HV Process
    • Basic input/output unit for a chip with digital core
    • Consisting of driver, receiver & pull-up/down resistors
    • According to PAD arrangement, classified into two groups: Inline I/O & Stagger one.
    • M31 also develops fail-safe or tolerance I/O for special application. The leakage current is inhibited when I/O power ramp down (Diagram A).
  • General IO at GF 130BCDLite2 Process
    • Basic input/output unit for a chip with digital core
    • Consisting of driver, receiver & pull-up/down resistors
    • According to PAD arrangement, classified into two groups: Inline I/O & Stagger one.
    • M31 also develops fail-safe or tolerance I/O for special application. The leakage current is inhibited when I/O power ramp down (Diagram A).
  • High-Speed Single-Ended to Differential Circuit
    • Linear CML stage, with 0dB Gain & BW > 28GHz
    • GlobalFoundries - 45SPCLO
  • High-speed IO termination cell
    • 100Ω differential, 4-bit tunable
    • GlobalFoundries - 45SPCLO
  • 2.5V 5V Tolerant GPIO Inline IO Pad Set
    • ? Fault tolerant operation – no current flow @ DVDD = 0V
    • ? 5V tolerant @ 3.3V operation
    • ? Multi-Voltage (1.8V, 2.5V, 3.3V)
    • ? Programmable drive strength (rated 2mA to 12mA)
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