Memory & Libraries IP for GLOBALFOUNDRIES
Welcome to the ultimate
Memory & Libraries IP
for
GLOBALFOUNDRIES
hub! Explore our vast directory of
Memory & Libraries IP
for
GLOBALFOUNDRIES
All offers in
Memory & Libraries IP
for
GLOBALFOUNDRIES
Filter
Compare
99
Memory & Libraries IP
for
GLOBALFOUNDRIES
from
20
vendors
(1
-
10)
-
1.8V/3.3V GPIO With I2C Compliant ODIO in GF 55nm
- This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity.
- The library includes 1.8/3.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD.
-
IO Library - GLOBALFOUNDRIES 22FDX
- Library contains approx. 60 IO cells
- Support for all metal-stacks of 22FDX®
- Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
- Low leakage cells for ultra low power always-on domain usage
-
Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
- The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
-
Dual Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
-
LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
-
LVDS Serializer IP
- The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
- The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
-
Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
- Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation.
- Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX® Platform solution.
-
5V ESD Clamp in GlobalFoundries 180nm LPe
- A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
- A key attribute of this 5V Clamp is that it can be used for either signal protection or 1.8V power supplies.
- The clamp is a single cell, 44um x 32um in size. It is built from the substrate to metal 6.
-
1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
- A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
- This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function.
-
3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
- A 3.3V wire-bond I/O library, a 1.2V ODIO and 5V tolerant ODIO.
- This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology.
- The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter.
