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Serdes IP for GLOBALFOUNDRIES

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Compare 15 Serdes IP for GLOBALFOUNDRIES from 8 vendors (1 - 10)
  • Ultra-short reach SerDes with 500 Gbit/s throughput
    • 2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
    • High pin-efficiency and low power
    • 208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)
    Block Diagram -- Ultra-short reach SerDes with 500 Gbit/s throughput
  • Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
    • Wide range of protocols that support networking, HPC, and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
    • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
    • Selectable serial pin polarity reversal for both transmit and receive paths
    Block Diagram -- Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
  • Multiprotocol SerDes PMA
    • Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
    • Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
    • Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
    • Core-voltage line driver with programmable pre-and post-emphasis
    Block Diagram -- Multiprotocol SerDes PMA
  • 4.25 Gbps Quad Multistandard SerDes
    • 1.0 to 4.25 Gbps operation per channel
    • 1.2V/2.5V power supply, CMOS design
    • Low power dissipation (80mW /channel at 3.2 Gbps)
    • Minimal external components
    Block Diagram -- 4.25 Gbps Quad Multistandard SerDes
  • Custom Programmable Low Power SERDES on GLOBALFOUNDRIES 65G
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.172 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 11 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
    • Data-rates from 8.5Gb/s to 11.3Gb/s.
    • Digital 32-bit input
    • Output CML 50Ω terminated
    • Output swing 400mV or 250mV p-p SE
  • Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
    • Data-rates from 8.5Gb/s to 11.3Gb/s.
    • High sensitivity input (15mV SE p-p)
    • Adjustable input signal equalizer
    • Clock and Data Recovery
  • Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
    • Data-rates from 8.5Gb/s to 11.3Gb/s.
    • High sensitivity input (15mV SE p-p)
    • Adjustable input signal equalizer
    • Clock and Data Recovery
  • 32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
    • Supports data rates of 2.5 to 32 Gbps
    • Optimized for low-power operation and north/south die-edge placement
    • AC-coupled RX front end with on-chip capacitors
    • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
  • 28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
    • Optimized for low-power operation and north/south die-edge placement
    • Duplex Lane configurations of x4 and x1
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