The Ethernet SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCI Express® (PCIe®), Ethernet and USB specifications. Available for both low-power mobile applications and high-performance computing applications, the Ethernet SerDes PHY IP is pre-integrated with Cadence controllers and equipped with extensive test features for superior interoperability and the lowest risk path to SoC success.
Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
Overview
Key Features
- Wide range of protocols that support networking, HPC, and applications
- Low-latency, long-reach, and low-power modes
- Multi-Link PHY—mix protocols within the same macro
- EyeSurf —non-destructive on-chip oscilloscope
- Extensive set of isolation, test modes, and loop-backs including APB and JTAG
- Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
- Selectable serial pin polarity reversal for both transmit and receive paths
Benefits
- Low Power: Low-active and low-leakage optimized design
- High Flexibility: Flexible lane configuration with multi-protocol multi-link support
- Comprehensive Testability: Extensive testability support for BIST, scan, loopbacks, SoC isolation, and on-chip eye plotter
Block Diagram
Technical Specifications
GLOBALFOUNDRIES
In Production:
12nm
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