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PCI Express Phy IP for GLOBALFOUNDRIES

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Compare 7 PCI Express Phy IP for GLOBALFOUNDRIES from 2 vendors (1 - 7)
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  • 12nm
  • PHY for PCIe 3.1
    • Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
    • Multi-protocol support for simultaneous independent links
    • Supports SRIS and internal SSC generation
    • Supports PCIe L1 sub-states
    • Automatic calibration of on-chip termination resistors
    • Supports internal and external clock sources with clock active detection
    Block Diagram -- PHY for PCIe 3.1
  • PCIe 2.0 PHY, GF 12LP+ x2 North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, GF 12LP+ x2 North/South (vertical) poly orientation
  • PCIe 2.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
  • PCIe 2.0 PHY, GF 12LP x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, GF 12LP x2, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
  • PCIe 4.0 PHY in GF (14nm, 12nm)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
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