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Finite Impulse Response IP

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Compare 17 Finite Impulse Response IP from 10 vendors (1 - 10)
  • ASIP-1 FFT Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions.
    Block Diagram -- ASIP-1 FFT Engine
  • ASIP-2 Programmable Filter Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2 Programmable Filter Engine
  • RGB to ITU-R 601/656 Encoder
    • The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
    Block Diagram -- RGB to ITU-R 601/656 Encoder
  • LMS Adaptive Channel Equalizer
    • 17-tap T-spaced complex-arithmetic LMS signed-error Channel Equalizer
    • Adaptation bandwidth control (mu, step size)
    Block Diagram -- LMS Adaptive Channel Equalizer
  • Multi Channel FIR Filter
    • Multi Channel FIR filter
    • Selectable data and coefficient widths
    • Selectable number of data channels
    • Selectable number of filter taps
    Block Diagram -- Multi Channel FIR Filter
  • Ultra-speed FIR Filter
    • Systolic array for speed and scalability
    • Configurable coefficients
    • Configurable data width
    • Configurable number of taps
    Block Diagram -- Ultra-speed FIR Filter
  • DAC Correction Filter
    • Efficient, multiplier-free design
    • Configurable input and output widths
    • Multiple tap-length configurations
    Block Diagram -- DAC Correction Filter
  • Serial FIR Filter
    • Serial Arithmetic for Reduced Resource Utilization
    • Variable Number of Taps up to 64
    • Data and Coefficients up to 32 Bits
    • Output Size Consistent with Data Size
    Block Diagram -- Serial FIR Filter
  • Parallel FIR Filter
    • Variable number of taps up to 64
    • Data and coefficients up to 32 bits
    • Output size consistent with data size
    • Zero-latency operation
    Block Diagram -- Parallel FIR Filter
  • Distributed Arithmetic FIR (DA-FIR) Filter Generator
    • Variable number of taps up to 1024
    • Multi-channel support (up to 32 channels)
    • Polyphase interpolation/decimation filters
    • Halfband filters
    Block Diagram -- Distributed Arithmetic FIR (DA-FIR) Filter Generator
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