Included in EDK at no additional charge starting in EDK9.2i
This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.
XPS IIC Bus Interface
Overview
Key Features
- Master or slave operation
- Multi-master operation
- Software selectable acknowledge bit
- Arbitration lost interrupt with automatic mode switching from master to slave.
- Calling address identification interrupt with automatic mode switching from master to slave
- START and STOP signal generation/detection
- Repeated START signal generation
- Acknowledge bit generation/detection
- Bus busy detection
- Fast mode 400 KHz operation or standard mode 100 KHz
- 7 bit or 10 bit addressing
- General call enable or disable
- Transmit and receive FIFOs - 16 bytes deep
- Throttling
- General purpose output, 1 bit to 8 bits wide
- Dynamic Start/Stop generation
Technical Specifications
Related IPs
- AXI IIC Bus Interface
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- I2C Bus Interface - Master with FIFO
- I2C V2 Bus Interface
- I2C Bus Master / Slave Controller Interface with FIFO
- Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s