PowerPC Bus Slave

Key Features

Fully supports PowerPC™ 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
Designed for ASIC or FPGA implementations in various system environments.
Direct support for standard asynchronous SRAM and synchronous BURST SRAM.
User interface bus for on-chip and off-chip user logic access.
Variable wait state supported on user logic.
Burst access supported on all interfaces.
Process memory requests on the PowerPC bus.
Handles separate address bus and data bus tenure.
Supports PowerPC address pipeline for improve performance.
Supports address bus retry generated by other external device.
Address parity and data parity detection and generation.

Short description

PowerPC Bus Slave

Vendor

Vendor Name

Availability

Now

UMC

Pre-Silicon: 500nm