VeriSilicon SMIC 0.18μm 1.8V/3.3V CFIO_01 Library
Overview
VeriSilicon SMIC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for SMIC 0.18μm 1P6M Salicide logic process. This library supports inline I/O pads design with four layers of metal. It can work under either 5V or 3.3V with configurable output driving strength.
Key Features
- SMIC 0.18μm Logic 1P4M Salicide 1.8/3.3V process
- Provides 5V/3.3v configurable output driving strength
- Provide CMOS or Schmitt trigger input buffer with weak pull up/down
- Provides power cut cells to abut against Generic IO library
- Suitable for four metal layers of physical design
Technical Specifications
Foundry, Node
SMIC 0.18um
Availability
GDS ready
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL
Related IPs
- VeriSilicon SMIC 0.18μm 1.8V/3.3V ANALOGIO_05 IO Library
- VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
- VeriSilicon UMC 0.18μm CF I/O
- VeriSilicon UMC 0.18μm CF I/O
- SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
- SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library