VeriSilicon UMC 0.18μm CF I/O
Overview
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II logic process. This library supports inline I/O pads. It can work under either 5V or 3.3V with configurable output driving strength.
Key Features
- VeriSilicon UMC 0.18μm CF I/O Cell (01) Library supports design with four, five, or six layers of metal.
Technical Specifications
Foundry, Node
UMC 0.18um
Maturity
available on request
UMC
Pre-Silicon:
180nm
Related IPs
- VeriSilicon UMC 0.18μm CF I/O
- VeriSilicon SMIC 0.18μm 1.8V/3.3V CFIO_01 Library
- VeriSilicon SMIC 0.18μm 1.8V/3.3V ANALOGIO_05 IO Library
- VeriSilicon SMIC 0.13μm 1.2V/3.3V VPPIO_DUP_01 IO Library
- VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library
- VeriSilicon CHRT 0.13um 1.2V/3.3V DUPIO_01 Library