Variable FFT (run time choice of FFT size)

Overview

This FFT circuit employs unique architectural characteristics, different than any other FFT implementation. In particular the locality, simplicity and regularity of the processing core keeps interconnect delays lower than cell delays, leading to clock speeds that can approach the FPGA fabric limitations, e.g., "worst case" Fmax speeds >500MHz in 65nm FPGA technology. Short critical path lengths also lower power dissipation. Additionally, a novel algorithm reduces the number of cycles needed per FFT to less than the transform size. Because the circuit is a "memory based" architecture it is programmable so that a range of transform sizes (even non-powers of 2) can be performed on the same array given adequate memory resources. Finally, it includes a low overhead hybrid floating-point feature that increases dynamic range for a given fixed-point word size.

Key Features

High Throughput: obtained from high clock rates (>500MHz using 65nm technology) and novel algorithms
FFT size: any user chosen set of power-of-two or non-power-of-two sizes chosen at run-time (e.g., 128/256/512/1024/2048 points for LTE/WiMax OFDMA)
Programmability: Simple control circuitry for matching circuit/application functionality and I/O interface.
Dynamic Range: combined block floating point and floating point architecture means smaller word lengths can be used for post-processing operations such as equalization.
Scalability: array based architecture means arbitrarily higher throughputs are obtained by increasing array size
Power: array interconnects are entirely local, reducing parasitic routing capacitance to keep power dissipation low
Data I/O: Streaming, normal order I/O with fixed-point 2’s complement input words

Benefits

Easily modified to meet application requirements
Non-power-of-two options
Can do cyclic prefix insertion for LTE and Wimax OFDMA

Block Diagram

Applications

wireless communications and broadcast protocols, LTE, WiMax, radar, advanced noise cancellation, signal processing

Deliverables

Netlist (e.g., for Altera FPGAs a *.qxp file for synthesis or a *.vo file for simulation)
Synthesis constraints (e.g., for Altera FPGA’s an *.sdc file)
Modelsim Testbench (*.vo file for DFT circuit plus verilog testbench for control). Matlab verification utilities also available.
Altera Stratix III FPGA board development kit testbench
Matlab behavioral bit-accurate model (p-code)
Documentation

Technical Specifications

Maturity

Hardware verified

Availability

Now

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