Fast and efficient two-dimensional FFT core for image processing applications

Successful FPGA/ASIC implementation of two-dimensional FFTs (used in 2D image processing applications) requires deep understanding of the underlying 1D FFT algorithm, chip and memory architectures. Since each pixel of image data is effectively processed twice, the issues of throughput, scaling, resource usage, and memory interfacing all become intertwined when considering the optimal solution for the target chip architecture