USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps

Overview

KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits. The PHY can be configured for either an 8-bit or a 16-bit parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480bps transfer rate, while remaining backward compatible with USB1.1 legacy protocol at 12Mbps.

It includes the following blocks:
* Analog Driver and Receiver
* PLL generate the 480MHz clock
* Clock and Data Recovery
* NRZI encoder/decoder
* Serialize / De-serialize
* Control state machine
* Integrated pull up and self-calibrated termination resistors and switches

Key Features

Complies with Universal Serial Bus Specification Rev. 2.0
Interface compliant with the UTMI specification (60MHz 8-bit interface or 30MHz 16-bit interface)
Supports 480Mbps High-Speed(HS) and 12Mbps Full-Speed(FS)
Serial data transmission rates
Built-In Self Test (BIST)
Integrated Self-Calibrated termination resistors (45 ohm) and built-in 1.5K ohm
Power supply: VDD33=3.3V ±10%, VP12=1.2V ±10%
Operating temperature: -40°C~ +125°C

Benefits

Physical layer transceiver (PHY), 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
Supports 480bps transfer rate, while remaining backward compatible with USB1.1 legacy protocol at 12Mbps.

Block Diagram

Applications

Digital Video camera
Scanner
Printer
External storage devices, e.g.Portable hard disk, Optical drive (CD-ROM, CD-RW, DVD)

Deliverables

Data Sheet
Integration guide
LEF
Timing LIB
Verilog PHY behavioral model and BIST test-benches
EVB schematic and user guide

Technical Specifications

Foundry, Node

Silterra 0.13um Generic Process

Availability

NOW

Request Info