KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and PIPE3 compliant digital interface.
KA13UGPEP20ST001 offers a modular architecture, diagnostic access, and testability support, in addition to low power and small area.
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
Overview
Key Features
- Support for 2.5Gbps/5.0Gbps data rate for PCIe1.1 and PCIe2.0
- Support Loop-back BERT and Loop-back
- Support Self-calibration for On-die-termination
- Industry standard PIPE2
- Full power management support
- Power saving modes support
- Support low-power transmitter
- Beacon transmit and detect
- Receiver detection
- Built-in 8B/10B encoding/decoding
- 16 bit data interface
- Single channel clock & data recovery, serial data transmit and serializer-deserializer
- Built-in self test
- Extensive test and diagnostic access modes
Benefits
- Support for 2.5Gbps/5.0Gbps data rate for PCIe1.1 and PCIe2.0, Loop-back BERT and Loop-back, and Self-calibration for On-die-termination
Technical Specifications
Foundry, Node
Silterra, 0.13um CMOS process
Availability
NOW
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