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UpScaler IP Core

Overview

Image scaling is not an easy task, especially when increasing the resolution. Quality of the scaled image is mainly dependent on the interpolation method by means of which the synthesis is performed for each pixel. The Lanczos methods and, a little lagging behind it on quality of the image, a method of bicubic interpolation are recognized as the qualitative methods of interpolation. Complexity and specifics of these interpolation algorithms complicates their use in the FPGA technology.

UpScaler IP Core implements the original algorithm. The quality is not inferior to the interpolation parameters of bicubic method but the complexity of the algorithm is close to linear interpolation.

UpScaler IP Core is intended for use in systems of display of video (wall video, displays, video projectors) but also can be applied in transcoding systems for media content preparing.

Key Features

  • The image quality on the PSNR metric scaling to more than 2 times is better than the bilinear interpolation on 6-8 dB and on 0.5-1 dB better than – bicubic interpolation method.
  • Supports RGB and YUV color spaces with an arbitrary bit color component (the bit is set the parameters of synthesis).
  • Output resolution both horizontally and vertically is not limited
  • The maximum input horizontal resolution is determined by the volume of the internal buffer and set the parameters of the synthesis
  • The maximum input vertical resolution is not limited. It only will affected on the performance.
  • Scaling coefficients arbitrary and can be changed dynamically.

Deliverables

  • IP Core is available as either netlist or VHDL source codes.
  • It includes all that requires for easy integration to the customer projects.
  • The delivery includes:
    • Netlist for target FPGA device;
    • Testbench;
    • Detailed specification and implementation guide.

Technical Specifications

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