UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
Overview
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
Technical Specifications
Foundry, Node
UMC 40nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
- 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
- Low Power PLL for TSMC 40nm ULP
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- Single Port SRAM Compiler IP, UMC 65nm SP process
- BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)