Offers new options for your design by supporting multiple configurations in a variety of applications
The PCIe DMA controller enables ultra-fast data transfer between FPGA logic, processors, and memory to meet the requirements of low-latency and datacenters requirements. User-friendly for software developers building low-latency network streaming applications. Easy to integrate with standard PCIe endpoint and Orthogone ULL TCP/IP, UDP/IP Offload Engine.
ULL PCIe DMA Controller
Overview
Key Features
- PCIe Gen 3 (x16)
- Ultra-fast transfer of data between FPGA logic and memory mapped user space
- Multi-channel circular buffer architecture
- Zero-copy circular buffers memory mapped to user space
- Integrated with Xilinx US+ PCIe IP core
- 250MHZ Core clock
Benefits
- Best in-class latency and throughput performances
- Custom multi-channel Circular Buffer DMA (CBDMA) architecture specifically designed for ULL applications
- Easy to integrate with standard PCIe endpoint (gen. 3, gen. 4)
- Full Kernel bypass implementation resulting in extremely low latency and jitter
- High-quality verification based on UVM environment
Technical Specifications
Related IPs
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- DMA Controller
- ISA / PC Card / PCMCIA CompactFlash Controller
- AMBA AHB Direct Memory Acess (DMA) Controller
- Compactflash/PCMCIA Slave Controller
- Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP