softDSP released 3GPP compliant Turbo decoder IP core in May, 2000. We also supply simulation program and C-source code, designer's guide, test vector, interleaver generation C source code. Powerful decoding performance and small-size implementation will meet your system requirements satisfactorily. softDSP Turbo decoder has the feature of easy I/O interface and used as a slave device controlled by host processor such as ARM core or any other DSP processor. It is recommended that every other part of 3GPP FDD blocks except Turbo decoder is implemented by s/w (dsp) for the such conditions as control oriented feature, easy updating, and development time reduction.
You may be working on system performance modeling, system implementation or you may require help with the implementation of a specific component. We work at all stages of the system design of channel coding and our expertise together with our hardware or software implementations will allow you to rapidly achieve your objectives.
Turbo decoder
Overview
Key Features
- Use max-log-MAP decoder as an internal component decoder which produces better performance than the other component decoder
- Use sliding-window technology to reduce internal memory size
- Constraint length K=4 (8-state with g0=1+D2+D3, g1=1+D+D3), rate 1/2, 1/3
- 4-8 bit soft input (recommend over 5bit input) with internal 8bit fixed-point processing
- Support 8-level Eb/N0 scaling
- 3GPP compliant (block size 40-5114)
- Easy to use interface, easy to modify or adapt
Deliverables
- VHDL source code
- Test C-source code (floating point and fixed point)
- Interleaver generation routine C-source (3G TS 25.212 V.3.2.0)
- Test data vector
Technical Specifications
Foundry, Node
FPGA
Availability
now