TSMC CLN3P 3nm General Purpose PLL - 400MHz-2000MHz
Overview
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.
Key Features
- Designed as a wide range clock multiplier with deskew capability.
- Delivers optimal jitter performance over all multiplication settings.
- Low area and low power.
- Suitable for system clock, DDR and general purpose applications.
- Ideal for cost sensitive applications.
Deliverables
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
Technical Specifications
Foundry, Node
TSMC CLN3P
TSMC
Pre-Silicon:
3nm
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