TSMC 40G 2Gb/s TX LVDS IO cell

Overview

Key Features

• TSMC 40 G
• 2.5V/0.9V IO/Core transistors
• Standard-compliant to TIA/EIA-644-A-2001
• Built-in, low parasitic ESD protection
• Easily integrates with TSMC I/O library cells
• All-in-ringR topology, so no core silicon area is used by LVDS
• The same cells operate with 2.5V/0.9V or 1.8V/0.9V power supplies
• Adjustable output common mode voltage (LVDS or SubLVDS mode)
• Adjustable driving current for buses with single or double termination
• Standby/power down mode
• Internal bias voltage generation and bias current distribution circuitry
• Selectable on-chip termination resistor, with optional user tuning
• Digital loopback functions to ease ATE testing
• Up to 2 Gbps data rate

Applications

• Multi-purpose reconfigurable IO
• Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
• Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
• Backplane high-speed data communications
• High-speed serial communications (HDMI, SATA, PCIeX, etc.)
• Communication to LCD/OLED screens
• Video sensor digital data interface

Deliverables

• GDS II layouts
• LEF abstracts
• CDL netlists
• Liberty timings
• Verilog description
• A full datasheet
• An integration note

Technical Specifications